All interfaces are documented in the core_top.v project template file. Check the HDL source for exact pin descriptions.
This type of pseudo-SRAM is a bit unique in that it can be accessed asynchronously with very low latency, but also be configured for 133mhz max speed synchronous bursts.
Each chip contains 2 separate dies with all signals wired in parallel except for the chip enables. Simple implementations can use the chip enable as an upper address bit.
Be careful to never assert both chip enable pins (CE0#, CE1#) to avoid bus contention.
Cores that that read/write often to PSRAM need to take note of a potential pitfall — each die’s configuration registers can be accessed via a specific read/write sequence to the last word of the die’s address space. While intended as a workaround for not needing to use the CRE pin, it presents a possible problem.
If the core’s usage pattern happens to exactly match this sequence (see page 19, “Software Access” on the datasheet) then both reads and writes in this area may result in unintended behavior. There are two PSRAM chips on Pocket, containing two dies each, for a total of 4 potential affected memory addresses.
Cores with possible usage patterns matching the Software Access sequence and also accessing these die’s highest location (word address 3FFFFFh) should instead special-case this address and use FPGA registers to store the value.
Standard asynchronous SRAM. Drive an address, strobe write enable or output enable. Latency is marginally faster than PSRAM but possible bandwidth is lower.
Standard synchronous DRAM. Comparable to PC133 SDRAM, except using a different voltage standard, its maximum frequency is increased to 166MHz. SDRAM is best accessed in bursts since every access requires activation and precharge overhead. DQM(H/L) are wired for byte-granular write masking.
Be mindful of the additional mode registers necessary to program during initialization. Consider referencing the industry-standard Micron 256M SDRAM datasheet for further details about how to use SDRAM.
Cores have complete access to the cartridge bus
core.jsonLeave all cartridge pins in the default settings per the template HDL unless actively using the port. If the level translators are improperly configured while cartridge power is turned on, a user may lose data from an inserted cartridge.
Pocket contains an infrared transmitter LED and receiver circuit.
Located in the same lightpipe as the power LED, the IR LED drive signal is active high. Because the LED is running near its maximum rated current, it should never be driven with DC. Only use PWM-type pulses to drive the LED at a duty cycle lower than 100%.
The receiver circuit has automatic gain control (AGC) to adjust for ambient light levels and expects to see typical PWM-type waveforms.
The receiver must be disabled whenever not in use as it consumes a nontrivial amount of power. Allow a few milliseconds for the AGC to stabilize when enabled.